1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method for testing a semiconductor memory device. For example, the present invention relates to a method for testing a semiconductor memory including a MOS transistor having a charge storage layer and a control gate.
2. Description of the Related Art
A day-to-day increase in the capacities of semiconductor memories has correspondingly increased the number of memory cells storing data. Each memory cell is manufactured through an enormous number of, for example, several hundred process steps. Thus, it is impossible to enable all memory cells to be produced in the same condition; manufacture of semiconductor memories involves a certain process variation.
Before semiconductor memories with such a process variation are shipped, defective bits are replaced with redundant bits or determined to be defective to prevent initially defective or unreliable products from being shipped. Thus, many electrical inspection steps are executed in a manufacture stage for semiconductor memories.
More accurate screening (sorting of defective parts) methods have been required in order to improve the reliability of increasingly miniaturized semiconductor memories. Various methods have been proposed which use a built-in self-test (BIST) circuit in a semiconductor memory to inspect the memory. Such a method is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-39226.
One of the screening methods is a search of isolated bits. The isolated bit means a memory cell having a threshold voltage deviating from the threshold distribution of all the memory cells (population distribution). Such a memory cell often has degraded reliability, and it is important to search for isolated bits for screening. However, it is very difficult to search for isolated bits by the conventional inspection methods.